CS 2071 COMPUTER ARCHITECTURE(2 marks with answers)

CS 2071                                 COMPUTER ARCHITECTURE

UNIT-I

1.     Define Digital computer.

                    It is a fast electronic calculating machine that accepts digitized input

          information, processes it according to a list of internally stored instructions,

          and produces the resulting output information.

2.     Mention the types of computers

·         Personal computer: schools, business offices, desktop

·         Portable notebook: used mainly for word processing, desktop

·         High performance workstations: graphics and I/O capability, higher  

         computational           power, desktop

·         Mainframes: business data processing in medium to large range

     corporations

·         Supercomputers: large scale numerical calculations.

3.     Illustrate Basic functional units of a computer with diagram.

	I/O		Processor

 

Input

Arithmetic and Logic

           

			Memory
					Output
	Output

 

4.     Define computer architecture.

Computer Architecture deals with the structure and behavior of a computer including the information formats, the instruction sets and various techniques used for memory addressing.

5.     Define Input Unit.

Computers accept coded information through input units(read data).

Example:  The keyboard is wired so that whenever a key is pressed, the corresponding digit is automatically translated to its corresponding code and sent to the memory or to the processor.

Other examples:  joysticks, trackballs and mice.

6.     What are the registers that communicate with the main memory?

Memory address register and memory data register are the registers that communicate with the main memory

7.     Explain Arithmetic and Logical Unit?

                    ALU is the heart of the machine.

•          All arithmetic operations such as addition, subtraction, multiplication and division is done here.

•          Logical operations such as AND, OR and NOT are also performed      

•          Operands and results of ALU operation could be located in register or in memory.

8.     Define IR and PC register.

IR register: holds the instruction that is currently being executed. The IR content is available to the control circuits which generate timing signals.

PC register: register that keeps track of the execution of a program, it contains that memory address of the next instruction to be executed.

9.     What is meant by MAR and MDR?

MAR: Memory address register, hold the address of the location to or from which data are to be transferred.

MDR: contains the data to be written into or read out of the addressed location.

10.    Define Bus with its types.                                                 [MAY/JUNE2012]

Bus is defines as a group of wires that connects several devices. Buses usually carry data, address and control signals.

Single bus:  All units are connected to this bus. Only two units can use the bus at any given instant. Low cost, can easily add new devices on the bus.

Multiple bus: Systems that contain multiple buses achieve more parallelism. It has a better performance at an increased cost.

11.    Define system software with its functions.

System software is a collection of programs that are used to perform the following functions.

·            Receive and interpret user commands.

·            Enter and edit application program.

·            Store files in secondary storage.

·            Manage the storage and retrieval of files in secondary storage.

·            Run standard applications such as spreadsheets.

·            Control I/O units to receive input information and produce results.

·            Translate programs from source prepared by the user into object

      form (machine instructions).

12.    What is meant by operating system?

The operating system (another system software) is a collection of routines used to control the sharing an interaction among different computer units.

13.    What are the two different schemes are used to place an individual byte without a word?

              Little endian :byte 0 is the rightmost byte of word 0

              Big endian :byte 0 is the leftmost byte of word 0

14.    Name the types of operations that a computer must perform using instruction?

A computer must have instructions capable of performing four types of operations

a.      Data transfers between the main memory and the CPU registers

b.      Arithmetic and logic operations on data

c.      Program sequencing and control

d.      I/O transfer.

15.       Define Three Address Instruction

Instruction that contains three address fields, each providing the address    

            of one of the operands. Three address instruction can be represented  

            symbolically as

             Add A,B,C

             Operands A and B are the source, operand C is the destination

             Operation Source1, Source2, Destination

16.       Name some of the Addressing modes. [MAY/JUNE 2013]

Register mode : the operand is the content of a CPU register named in  

            the instruction

               Absolute mode : the operand is in a memory location given explicitly in

        the instruction

               Immediate mode: the operand is given explicitly in the instruction

              Move 200immediate, R0

              Move #200,R0

                    Indirect mode: the effective address of the operand is the content   

  of a register or a main memory location. The location whose address appears   

  in the instruction. The register or memory location that contains the address    

  of the operand is called a pointer

17.       What is floating point numbers?

In some cases, the binary point is variable and is automatically adjusted

   as computation proceeds. In such cases, the binary point is said to be float  

   and the numbers are called floating point numbers.

18.       Name the three systems used for representing both positive and

  negative numbers.

a.      Sign and magnitude.

b.      1’s complement

c.      2’s complement

19.       What is meant by overflow?

a.         When adding unsigned numbers, the carry-out c_n serves as the overflow indicatorthis does not work for adding signed numbers

Example: adding +7 and +4 in 4-bit adder, the output vector S = 1011 = -5 and the carry-out signal from the MSB is 0

b.      add -4 and -6 , S = +6, and the carry-out signal is 1

The addition of numbers with different signs cannot cause overflow because the absolute value of the sum is always smaller than the absolute value of one of the two summands

20.       Define Booth Algorithm.

Booth Algorithm is a powerful algorithm for signed-number  

   multiplication. It generates 2n-bit product and treats positive and negative    

   numbers uniformly.

21.       What are the two types of Division Algorithm

a.      Restoring Division

b.      Non Restoring Division

22.       Write the restoring division algorithm.

Shift A and Q left one binary position.

Subtract M from A, and place the answer back in A.

If the sign of A is 1, set q0 to 0 and add M back to A(ie, restore A);otherwise, set  q0 to 1.

23.       Write the non-restoring division algorithm.

a.         Step 1: Do the following n times:

If the sign of A is 0, shift A and Q left one bit position and subtract M from A; otherwise, shift a and Q left and M to A.

Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.

b.         Step 2: If the sign of A is 1, add M to A.

24.       Mention some of the Exceptions.

a.         Invalid operation, division by 0, overflow, underflow and inexact

25.       Write the rules for floating point arithmetic operations.[AU-Nov 2008]

Add/subtract

a.         choose the number with the smaller exponent and shift its mantissa

      right a number of steps equal to the difference in exponents

b.         set the exponent of the result equal to the larger exponent

c.         perform addition/subtraction on the mantissas and determine the

      sign of the result

d.         normalize the resulting value

Multiply

e.         add the exponents and subtract 127

f.          multiply the mantissas and determine the sign of the result

g.         normalize the resulting value

Divide

h.         subtract the exponents and add 127

i.           divide the mantissas and determine the sign of the result

j.           normalize the resulting value

26.       Name the three truncation methods.

                                               i.            Chopping.

                                              ii.            Von Neumann rounding

                                            iii.            Rounding.

27.       Define chopping.

There are several ways to truncate .The simplest way  is to remove the guard bit and maker no  changes in the retained bits. This is called chopping.

28.       Name the types of Adder.

a.         Fast adder

b.         Full adder

c.         n-bit ripple carry adder

d.         Carry lookahead adder.

29.       What is Bit Slice processing? & what are the two types of ALU expansion?

a.            The ALU can be easily designed for expansion to handle operands of

       size n=km or word size n>m.

b.            Spatial expansion and temporal expansion.

30.       What is overflow and underflow?

       A floating-point operation causes overflow or underflow if the result is too large or too small to be represented Shifting the mantissa of the result and modifying its exponent correct the overflow and underflow resulting from the mantissa operations.This is done automatically during the floating point processing.  However exponent overflow or underflow causes an error signal generation.

31.       What is guard bit?

       To preserve accuracy during floating point calculations one or more extra bits called guard bit are temporarily attached to the right end of the mantissa.

    

32.       Write the rule for addition and subtraction of floating point numbers.

[MAY/ JUNE 2013]

·            Choose the number with the smaller exponent and shift its

 mantissa right a number of steps equal to the difference in   

 exponents.

·            Set the exponent of the result equal to the larger exponent.

·            Perform addition/subtraction on the mantissas and determine the

 sign of the result.

·            Normalize the resulting value, if necessary.

                  

33.        What are the Condition codes?                         [AU-Nov 2008]

a.         The processor keeps track of some information about the results of various operations for use by subsequent conditional branch instructions. This information is recorded into bits called condition code flags.

b.         Eg. Carry, Zero, Negative, Parity and overflow

34.        What is meant by a word?

       Main memory is organized so that a group of n bits can be stored or retrieved in a single basic operation. Each group of n bits is called a word.

35.       Mention the registers used for communication between processor and                                    

   main memory.                                                                   [AUT, cbe – May 2010]

       Instruction Register, Program Counter, Memory Address Register, Memory Data Register and General Purpose Registers.

36.       Compare CISC and RISC with respect to complexity. [AUT, CBE– May 2010]

              RISC:

          Instructions are executed by hardware

          Complexity is in the compiler

                 CISC:

                           Instructions are executed by micro program

                           Complexity is in the micro program

37.        Give an example on Index addressing mode.  [AUT, CBE–May 2010]

       The effective address of the operand is generated by adding a constant value (in the instruction) to the content of a register.

            Example: Mov 20 (R1),R2

It loads the content of register R2 into the memory location 20+content of R1.

38.           What do you mean by straight line sequencing?[AUT,CBE–May 2010]

Execution of the program is started by placing address of first instruction  into PC. The processor fetch the instruction using content of PC and execute instructions, one at a          time, in the order of increasing addresses. This is called straight line sequencing.

39.           Differentiate direct and indirect addressing mode.[AU-Nov 2008]

        Direct: The address of the operand is given explicitly as part os the  

 instruction.

            Eg. Mov A, 2000

Indirect: The effective address of the operand if calculated by adding constant value to the content of a register.

              Eg. Mov 20 (R1),R2

40.           In floating point numbers when do you say that an underflow or

         overflow has occurred?

     In single precision numbers when an exponent is less than -126 then we say than an underflow has occurred. Single precision numbers when an exponent is less than +127 then we say that an overflow has occurred.

41.           Define Datapath.                                                              [MAY/JUNE 2010]

     A data path (also written as data path) is a set of functional units that function to process data. The central processing unit (CPU) in a computer contains data paths that route data between these functional units. A larger data path can also be created by joining data paths together using multiplexers.

42.           What are the steps to be considered while designing the instruction  

     format?                                                                               [NOV/DEC 2011]

·         Short instructions are typically better because they take up less space  

     in memory and can be fetched quickly.

·         Instructions of a fixed length are easier to decode but waste space.

·          Memory organization affects instruction format.

·         A fixed length instruction does not necessarily imply a fixed number

    of operands.

·         There are many different types of addressing modes like direct and  

          indirect.

43.          Define Index Mode.

     The Effective Address of an operand is generated by adding a constant value to the contents of a register.

Index Register: The register that is used to hold the constant value is indexed mode of addressing is called Index Mode is symbolically represented as X (Ri)

    Constant name of the register value  (offset)

EA =  X + [Ri]  

Offset value is also called displacement.

44.          What is the role of program counter in addressing?

     PC - Program Counter – Contains the memory address of the next instruction to be fetched and the execution of an instruction, the contents of the PC are automatically incremented.

45.          Discuss the following address modes with an example : Relative ,  

    Register and indirect

1.            Register mode

                        The operand is the contents of a processor register. The name of the register is given in the instruction.

2.            Indirect mode

              Effective address:     The actual memory address of the operand 

              Indirect mode:         The effetely address of the contents of a register /memory location whose address appears in the instruction. 

Example :         

   Fig 2.12, Fig 2.11

                 Add (R2), RO

The Register R2 contains the address of the operand.

Consider an operand stored at location 1000.  This value 1000 is stored in the register R2.

3.            Relative Addressing

               Special case of Indexed Mode where the index register is replaced with program counter.

              Relative mode: The effective address is determined by the index mode using the program counter is place of the general purpose Regular Ri.

              This mode is commonly used to specify target address in the branch instructions.

Additional Modes

-                Autoincrement mode

-                Autodecrement mode.

46.          Mention the four phases of an instruction cycle

·            Instruction Fetch

·            Instruction Decode

·            Instruction Execute

·            Write Results

47.          Specify the sequence of operations involved when an instruction is executed

·         Data transfers between the memory and the processor registers

·         Arithmetic and Logic operations

·         Program sequencing and control

·         I/O transfer

48.          What do you think the different factors to be considered while designing the instruction format?

·         Memory is byte addressable

·         Word length is 32 bits

·         Only one memory operand is allowed for each instruction and the  

     computer has a number of processor registers.

·         Each instruction is 4 bytes long (i.e.) if the first instruction is at

         location i, second instruction is at i+4, 3^rd at i+8 and soon.

49.          What is load-store architecture? Discuss

Load	Store
-          Transfer a copy from memory to processor -          Original data remains unchanged -          Processor sends the address of the desired location to memory.  Memory reads the data and sends them to the processor.	-          Transfer an item from processor to memory -          Original contents are lost -          Processor sends the address of desired location and the data to be written into that desired location.

50.          Explain the absolute and auto–increment addressing modes with an

    example instruction

Absolute mode

              The operand is in a memory location. The address of this location is given explicitly in the instruction. This mode is also called direct mode.

51.          State and explain CPU performance equation.

The basic performance equation is given by

                                            N x S

                                   T = -----------

                                              R

Where

‘T’ is the processor time required to execute a program written in a high level language

‘N’ is the actual number of instruction executions (not necessarily equal to the number of instructions in the object program)

‘R’ is the clock rate in cycles / second

‘S’ is the average number of basic steps needed to execute one machine instruction

52.          Registers R1 and R2 of a computer contain the decimal values 1200     

        and 4600.Indicate the addressing mode and find the effective

        address of the memory operand in each of the following instructions:

                   Move 20(R1), R5

     Load #3000, R5

                   Store R5, 30(R1) (R2)

     Add – (R2), R5

53.          Give an example of zero-address , one-address ,two-address and  

         three-address instructions

·               One Address instruction

       eg : Add A

            l® Add the contents of the memory location A with the contents of the Accumulator and place the result in the Accumulator.

·               Two Address instruction

       eg : Add A, B

       Add A, B, C is equivalent  ® Add A, B 

       Add the contents of A, B and Place the result in B.

·               Three Address instruction

       eg : Add A, B, C

54.          Define Big Endian and Little Endian.

·            Big-endian is used when lower byte addresses are used for the

      more significant bytes (the leftmost bytes) of the word.

·            Little-endian is used for the opposite ordering, where the lower

      byte addresses are used for the less significant bytes (the rightmost  

      bytes) of the word.

55.          Write IEEE standard for floating point format. Mention  the scale factor

IEEE Standard for Floating Point numbers:                

     Declare both the representation and the way in which the four arithmetic operations are to be performed.

                          ß--------------32Bits----------------------------------à

S

E’

M

                                           |_____|   |___________________________|

                                               |                                 |

                           { 8 bit signed exponent             {23 Bit}

                            in excess -127 representation}

            value= + 1.Mx 2^E’-127 .

            E’=E+127.     E’ is the ratio    0<E’<225.

0 and 225 are used to represent special values. Therefore E’ for normal values    1<E’<254.

56.           Discuss the principle of operation of a carry save adder.

1.         In CSA, each FA can handle 3 inputs.  Hence the partial products are

      divided into groups consisting of three.

2.         The results of three input addition (Sum and Carry) are added with

       the remaining results.

3.         The whole process is repeated until there is no result (or input) left

              out.

57.           What is the purpose of guard bits in floating point operations?

     Guard Bit:

              Although the operands’ and the results’ Mantissas are limited to 24 bits, it is important to retain extra bits (guard bits) during the intermediate steps to yield greater accuracy.

58.           What are the operations of a computer?

·            The computer accepts information in the form of programs and

      data through an input unit and stores in the memory.

·            Information stored in the memory is fetched, under program

      control, into an arithmetic and logic unit, where it is processed.

·            Processed information leaves the computer through an output unit

·            The control unit directs all activities inside the machine.

59.           Give the circuit of a full adder.

                                                   xi        yi

Full adder

                                  Ci+1

                                                     ci

                                    si

60.           What are the features of the Booth algorithm?

·            It handles both positive and negative multipliers

·            It achieves some efficiency in the number of additions required when

      the multiplier have a few large blocks of 1s.

16 marks

1. Explain the different types of addressing modes with suitable examples
2. Explain one, two, three addressing instructions with example
3. Explain in detail the different instruction types and instruction sequencing.
4. With a neat diagram explain Von Neumann computer architecture
5. What are the various types of Instruction set Architectures (ISAs) possible? Discuss.
6. Describe the functional units of the computer system.
7. Describe in detail Booth’s algorithm and its hardware implementation with suitable example
8. Explain restoring and non-restoring division method with own example.
9. Enumerate ALU design.

UNIT-II

1.     Define Fetch and Execution phase.

          Fetch Phase

Fetch the contents of the memory location pointed to by PC and load it into IR : IR    ß [[PC]]. Increment the content of the PC : PC ß [PC] + 1

          Execution phase

                   Carry out the instruction specified in the IR

          If an instruction occupies more than one word, the fetch phase must be repeated

2.     What is meant by asynchronous transfer?

           One device initiates the transfer and waits until the other device responds, It

      enables transfer of data between two independent devices that have different

      speeds of operation

3.     How can we performing an Arithmetic or Logic Operation?

          ALU is a combinational circuit that has no internal storage. To add two

      numbers, the two operands have to be available to the ALU simultaneously 

      Register Y holds one of the two numbers the other number is gated onto the bus

      and the result is stored temporarily in Z.

4.  Explain an execution of a complete instruction with example/steps required to execute the add instruction.                                 [Nov/Dec 2011]

           Example : Add  (R3), R1

           fetch the instruction:

o        PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin

o        Load the content of the PC into MAR, and send a read request 

o        while waiting for a response, increment PC

§         set one of the ALU registers (Y) to 0

§         set the other to the current value in PC,

§         set the carry-in = 1

§         specify Add operation

§         move updated value back into PC: Zout, PCin, WMFC

o        incrementing the PC using the adder circuit of the ALU, this is not the fastest approach, the PC can be implemented as a counter.

o        word fetched from memory is loaded into IR : MDRout, IRin

·         fetch the first operand : the content of the memory location pointed to by R3

o        R3out, MARin, Read

o        R1out, Yin, WMFC

·         perform the addition

o        MDRout, Add, Zin

·         load results into R1

o        Zout, R1in, End

5.       Write any two advantages of using Nano programming.

         [AUT,CBE–May  2010]

·         Reduce total size of required control memory

·         Greater design flexibility

6.       State the advantages of hardwired control unit.[AU-Nov 2008]

·         High speed

·         It uses less chip area

·         RISC microprocessor uses hardwired control.

7.       What are the address sequencing capabilities required in control      

          memory?

Each microinstruction should explicitly or implicitly specify the next instruction  to be used. Such address sequencing capabilities are required in a control memory.

8.       What is meant by microprogramming?

It is a method of control unit design in which the control signal selection and sequencing information is stored in a ROM or RAM called control memory.

9.       List out some advantages of micro programmed control?

·      Simple design

·      Control functions are implemented in software rather than hardware.

·      More flexible

·      Complex functions are realized easily.

10.     Compare horizontal and vertical organization in control signals.

Horizontal:

·         Long formats

·         Ability to express a high degree of parallelism

·         Little encoding of the control information

·         Useful when higher operating speed is desired

Vertical:

·         Short formats

·         Limited ability to express parallel micro operations

·         Considerable encoding of the control information

·         Slower operating speeds

11.    How to transfer the contents of R1 to R4?    [AU-CBE May 2010]

Activate the output enable signal of R1, R1out=1. This places the content of R1 on the bus.

Activate the input enable signal of R4, R4in=1. This loads data from the bus to R4.

12.    What are control signals needed to activate for Mov (R2),R1?

                  1. R2out, MARin

               2. R1out, MDRin, Write

               3. WMFC             

13.     Why we need MFC control signal?

In case of slow memory, the processor has to wait until the completion of 

  memory operation before going to perform next operation. In such cases

  control signal MFC(memory function completed) is used.

14.    Write the features of multiple bus organization.  [AU-CBE May 2010]

·      More than two devices can communicate at a time

·      Rate of data transfer increases

·      It reduces the execution time

15.    What is meant by micro-operations?

The processor unit has to perform some operations for fetch, decode and execute instructions. These operations called micro operation.

16.    What are the sequences of operations needed to perform subtraction?

                  R1out, Yin

                  R2out, Select Y, Sub, Zin

                  Zout, R3in.

17.    What are the basic operations performed by the processor?

Fetch the contents of the memory location pointed to by the PC. The contents   of this location are interpreted as an instruction to be executed.

        Increment the PC

        Execute the instruction in the IR.

18.    Define latency and throughput.

Latency: Each instruction takes certain amount of time to complete. ie time difference between when an instruction is issued and when it is completed.

                  Throughput: Number of instructions completed in a given time.

19.    What do you mean by hardwired control?

Hardwired control is implemented with gates, flipflops, decodes and other digital circuits. The goal is generate control signals with minimum number of components and maximum the speed of operation.

20.    What is nano control memory?

Micro instructions are used to access a control memory called nano control memory that directly controls the hardware.

21.    What is meant by hard wired control?

Hardwired control - using hardware to control the timing of control signals.

The required control signals for any operation is determined by,

- Contents of the control step counter

- Contents of the instruction register

- Contents of the condition code flags

- External input signals, such as MFC and interrupt requests.

22.    Differentiate hardwired and micro programmed control.

·         Hardwired control- using hardware to control the timing of control  

     signals.

·         Microprogrammed Control- using software (microprogram) to control  

     the timing of the control signals.

23.    Discuss briefly the basic organization of a micro programmed control

     unit.

·         The control signals are controlled by a program.

·         The starting and Branch Address generator generates the starting and      branch addresses on demand.

-These addresses are loaded into the micro program counter.

-The micro program counter is incremented every time a new micro  

  instruction is fetched except under the following situations:

·         When a new instruction is loaded.

·         When a branch instruction is encountered.

·         During an End instruction.

24.    What are the relative merits of horizontal and vertical microinstruction

     formats?

HORIZONTAL ORGANIZATION	VERTICAL ORGANIZATION
1. Minimally Encoded scheme in which many resources can be controlled with a single micro instruction.	1. Highly encoded scheme that use compact codes to specify only a small number of control functions in each microinstruction.
2. Used when a higher operating speed is desired.	2. Slower operating speed, because more microinstructions are needed to perform the described control functions.
3. Used when the machine allows parallel use of resources.	3. Does not imply that the total number of bits in the control store is smaller. Means that less hardware is needed to handle the execution of microinstructions.

       

16 marks

1.      Explain in detail the working of a micro programmed control unit

2.      Explain the various design methods of hardwired control unit.

3.      Explain the execution of a complete instruction.

4.      Draw and explain the multiple bus organization. Explain its advantages.

UNIT – III

1.           Define pipelining.                                                       [AU-Nov-2009]

          Pipelining is used to overlapping the instruction execution. It reduces the overall processing time.

2.           Name the steps in pipelined processor?

                    A pipelined processor may process each instruction in 4 steps

                    F: fetch, read the instruction from memory

                    D: decode, decode the instruction and fetch the source operands

                    O: operate, perform the operation

                    W: write, store the result in the destination location

          Four instructions are in progress at any given time, each unit operates on different data and the result is passed downstream through a storage buffer.

3.           What is meant by hazards? Mention its types.

[APRIL/MAY 2011][NOV/DEC 2011]

                    Any condition that causes the pipeline to stall is called a hazard.

          The different types of hazard which would occur are

          Data hazard,  Control hazard (instruction hazard) and  Structural hazard

4.           Define instruction pipeline.

          The type of pipeline which works by partitioning the instruction execution is called Instruction Pipeline

5.           What is a pipeline hazard? [MAY / JUNE 2013]

          In a pipelined environment when the next instruction cannot be executed in the following machine cycle, that situation is called hazard in pipeline.

6.           Define data hazard.    [AU - Nov 2008] [MAY / JUNE 2013]

          It occurs when an instruction is waiting for adapt that is not yet available because the previous instruction has not completed.

7.           Define control hazard? [MAY / JUNE 2013]

          It occurs due to branch instruction since the branch condition and the branch address are not available in time to fetch the next instruction on the next clock cycle.

8.           What is instruction level parallelism?

          Pipeline increases performance by overlapping execution of independent instructions.  The potential to overlap instructions is called Instruction-level parallelism     since the instructions are evaluated in parallel.

9.           What is Name dependence?

                   Name dependence is said to occur when two instructions use the same register or memory   location and there is no flow of data between instructions that uses the same name.

10.       Give some feature of superscalar processor

1) Smaller code size    

2) Binary compatibility across generations of hardware

3) No hardware changes required.

      

11.       What is data path implementation?

                   The design of data path involves decision at several levels of abstraction.  The control signals from the interface between the data path and the control unit, and is thus an important part of data path design and used to implement them.  This is data path implementation.

12.          What are the methods used to design a control unit?

                     Hardwired Control Unit

                 Micro programmed control Unit.

13.          Mention the data hazards that occur during pipeline operation.

                                                                                       [AUT,CBE–May 2010]

                    Write after Read hazards (Anti dependences hazards)

                    Read after Write hazards (Flow dependence hazards)

                    Write after Write hazards (Output dependence hazards)

14.             What are the factors to be considered while deciding number of pipeline stages in a system?                                                 [AUT,CBE–May2010]

The n-stage pipeline may get more throughputs by using more number of stages. When you are increasing number of stages, probability of the pipeline to be stalled increases. As the number of pipeline stages increase, the branch penalties may becomes more significant.

15.             List out techniques used to overcome data hazards.  [AU- Nov 2008]

·         Operand forwarding

·         Compiler can rearrange the instructions to avoid data hazards

16.             List any two conditions when a processor can stall.

                    Cache miss

                    Hazard in pipeline

17.          Define stall.

                    Idle periods are called stalls. They are also named as bubbles in pipeline.

18.          What are the problems faced in the instruction pipeline?

                    Resource conflicts

                    Data dependency

                    Branch difficulties

19.          Give an example for pipelined processors.

                    8086, 8088, 80286, 80386, STAR 100.

20.          Write down the equation for speedup factor in a pipelined architecture.

                    S= (K+n-1) t

                    K-number of segments

                    n-number of instructions to be executed

                    t-cycle time

21.          What is branch prediction? [MAY / JUNE 2013]

It is a technique for reducing the branch penalty is to predict whether or not a particular branch will be taken.

22.          What are the techniques used to present control hazard?

                    Scheduling instructing in delay slots

                    Loop unrolling

                    Conditional execution

                    Speculation

23.          What is deadlock?

A deadlock is a situation that can arise when two units A and B use shared resource. Unit B cannot complete its task until unit A completes. At the same time unit B assigned a resource that unit A needed.

24.          Why we need of an instruction buffer in a pipelined CPU.

In order to increase the computational speed of the pipeline processor the instructions are fetched in advance and will be placed in the instruction buffer.

25.          What are the types of dependences?

                    Data dependence

                    Name dependence

                    Control dependence

26.          What are the different types of exceptions may occur while executing an instruction?

                    Invalid operation, Overflow

                    Underflow, Zero divide

                    Denormalized operand

                    Inexact result

27.          List the basic steps in pipelining.                        [AU-MAY 2012]

                    Fetch

                    Decode

                    Execute

                    Store

28.          What is Structural hazard?                                      [AU-MAY 2012]

If some combination of instructions cannot be accommodated because of a resource conflict, the machine is said to have a structural hazard.

29.          State the different types of hazards that can occur in a pipeline.

            Three types of hazards:

1.       Data Hazard

2.       Instruction Hazard or Control Hazard

3.       Structural Hazard

30.          How do control instructions like branch, cause problems in a pipelined processor?

The time lost as a result of a branch instruction. One way of reducing the branch penalty is to compute the branch address earlier in the decode stage, rather than in the execute stage. This requires additional hardware.

31.          What is the ideal speedup that can be expected in a pipeline with k stages?

 Pipelined Machine (k stages)

t_p:   Clock cycle (time to complete each sub -operation)

t_k:   Time required to complete the n tasks

t_k = (k + n - 1) * t_p

  Speedup

S_k:   Speedup

         S_k = n*t_n / (k + n - 1)*t_p

      

32.       What are the difficulties caused by instruction pipeline do deviate from normal operation?

Any condition that causes the pipeline to stall is called a hazard.

                    Three types of hazards:

1.       Data Hazard

2.       Instruction Hazard or Control Hazard

3.       Structural Hazard

33.          How do control instructions like branch, cause problems in a pipelined processor?

·                        The branch address is computed only in the execute stage of a branch instruction. By that time, the fetch of the successive instruction would have been completed.

·         Thus the execution unit remains idle for one cycle and then the instruction at the branch target address is fetched.  This causes the instruction to stall for one cycle.

34.          What are the steps to execute an instruction?

Step 1: Fetch instruction

Step 2: Decode instruction and Fetch Operands

Step 3: Perform ALU operation

Step 4: Access memory

Step 5: Write back result to register file

Step 6: Update the PC

35.          What is clock cycle?

A clock cycle, or simply a "cycle," is a single electronic pulse of a CPU. During each cycle, a CPU can perform a basic operation such as fetching an instruction, accessing memory, or writing data. Since only simple commands can be performed during each cycle, most CPU processes require multiple clock cycles.

36.          What is control signal?

A pulse or frequency of electricity or light that represents a control command as it travels over a network, a computer channel or wireless. In the data communications world, control signals typically travel the same path as the data either as separate packets or contained within the data packets. In the traditional telephone communications world, control signals are sent over a separate network

37. Define micro routine and micro instruction.

          Microroutine: sequence of CWs (control word) corresponding to the control  

     sequence of a machine instruction0

          Microinstructions individual control words are called microinstructions 

38. Define PLA.

          PLA is used initially to decode the instruction OP codes one bit in the

     microinstruction is used to indicate when the output of the PLA is gated into the      

     mAR

39. What are the problems with prefetching?

     1. Next microinstruction may depend of the status flags and results of current

         microinstruction

     2. Prefetch the wrong microinstruction

          3. Fetch must be repeated with the correct address

40. How the required control signal are uniquely determined in hardwired control?

          With the help of following information.

·         content of the control step counter

·         content of the instruction register

·         content of the condition code and other status flags (eg. MFC status signal)

41. Define Microprogrammed control.[AU-MAY 2012][Nov/DEC 2011]

     It is a scheme in which control signals are generated by a program similar to machine language programs. A CW (control word) is a word whose individual bits represent the various control signals .

42. Write a micro routine for executing the instruction branch less than 0.                       

         [AUT, cbe–May 2010]

              PCout, MARin, Read, Yin, SelectC, Add, Zin

              Zout, PCin,WMFC

              MDRout, IRin

              Branch to starting address(eg. 45) of appropriate micro routine

              If N=0 then branch to microinstruction 0

              Offset field of IRout, SelectY, Add. Zin

              Zout, PCin,End

16 marks

1. Explain the basic concepts of pipelining and comparing it with sequential processing. Draw needed diagrams
2. Explain the various pipelining hazards and their remedies in the processor
3. What is branch hazard? Describe the methods for dealing with branch hazards,
4. What is data hazard? Explain the methods for dealing with the data hazards.
5. Highlight the solutions of instruction hazards
6. Explain instruction hazards.
7. Describe exception handling and data path considerations.

          

UNIT-IV

1.      Classify the memory components of a system.

·Internal processor memory

·Main memory

·Secondary memory

·Caches

2.        What is meant by cache memory?

A small and fastest memory that is constructed of very high-speed devices (flip-flops and gates SRAM) and added to the processor to reduce its memory access time

3.        What are the objectives of memory design?

·         To provide adequate storage capacity

·         To design a memory system with an acceptable level of performance

·         Reasonable cost

4.        What are the reasons for using virtual memory?           [AU-Nov 2009]

·        To free the programmers from the need to carry out storage allocation

·        To permit efficient sharing of memory space among different users

·        To make programs independent of the configuration and the capacity of the memory systems.

·        To achieve high access rates and low cost per bit.

5.        What is block contention problem?

The problem suffered by direct mapping method in which one or more frequently used block occupies the same block in cache memory even if unused blocks are available

6.        Define EPROMS

·Allows stored data to erased and new data to be loaded

·Erasable reprogrammable ROM (EPROM)

·Provide flexibility during the development phase of a digital system

·Erasure requires the dissipating the charges trapped in the transistors

·This can be done by exposing chip to ultra violet light

·A disadvantage of EPROMs is that a chip must be physically removed  

   from the circuit for reprogramming

7.        Define EEPROMS

An alternative to EPROMs, they can be programmed and erased electricallyCells in EEPROMs can be erased selectively.

Disadvantage of EEPROMs: different voltages are needed for erasing, writing and reading stored data

8.        Differentiate temporal spatial locality.

Temporal locality

·         suggests that whenever an item (instruction or data) is  first needed,

·         this item should be brought to the cache where it hopefully remains until it is needed again

·         Spatial locality

·         suggests that instead of bringing one item from main memory, it is wise to bring several items that reside in adjacent addresses as well

·         block or cache line : is used to refer to a set of contiguous addresses

9.        What is meant by read miss in cache?

·         the addressed word is not in the cache

·         after the entire block is loaded into the cache, the particular word requested is forwarded to the CPU

·         alternatively, the word may be sent directly to CPU as soon as it is read from main memory : load through or early restart

10.       What is meant by replacement algorithm?

When a new block is to be brought into the cache and all the positions that is may occupy are full, the cache controller must decide which of the old blocks to overwrite

11.       What are the different types of interrupts?

• Interrupts may be external or internal
• Hardware and software interrupts are also raised
• Interrupts are raised by power failure conditions, divide by zero etc.
• Masking and enabling of these can also be done.

12.       Mention the advantage and Disadvantage of Direct mapped Cache.

               Advantage:

·         Simple to implement

               Disadvantage:

·         Suffers from block contention problem – If one or more frequently used block occupies the same block in CM even if unused blocks are available

·         Not very flexible

13.       Define the technique FIFO and LRU

1. FIFO – removes the oldest block simple - but frequently used block is removed if oldest
2. LRU  – removes the block that has not been referred for the longest period of time -better – more difficult to implement

14.       Differentiate SRAM and DRAM. [AU-Nov-2008]

SRAM	DRAM
q      Bits stored in flip-flop q      No charges to leak q      No refreshing needed when powered -   does not need refresh circuits, does not waste time refreshing q      More complex cell– more transistors per cell q      Larger per bit q      More expensive q      Faster q      Used for cache memory	q      Bits stored as charge in capacitors q      Charges leak in milliseconds q      Need periodic refreshing even when powered – read, rewrite by CPU q      Need to refresh → ‘dynamic’ RAM q      Simpler construction but need refresh circuits q      Smaller per bit q      Less expensive q      Slower q      Used for main memory

15.       Define memory Latency.                                           [AU-MAY 2012]

          Time taken to transfer a single word of data to or from memory. Definition is clear if the memory operation involves transfer of a single word of data. In case of a block transfer, latency is the time it takes to transfer first word of data. Time required to transfer first word in a block is substantially larger than the time required transferring consecutive words in a block.

16.        What is meant by memory interleaving? [AU-Nov 2008] [AUT, CBE –May 2010] [MAY / JUNE 2013]

          Memory interleaving is used to reduce the memory access time. The main memory is divided into modules and the addresses are arranged such that successive words in the address space are placed in different modules.

17.       How read and write operation is performed in static memory.

[AUT, CBE–May 2010]

          Read operation:

                   It enabled by R signal high. Thus connects the output data line to the data out .Thus complement of the bit stored in the cell is available at the output.

          Write operation:

                   It enabled by W signal high. If data-in signal is logic1, node D is also at logic 1. This turns ON T2 and T1 is cut-off. If new data on data-in pin is logic 0, T2 will be cutted off and T1 will be ON.

18.       What is virtual memory?

Virtual memory is used to increase the apparent size of the physical memory. Data are addressed in a virtual address space that can be as large as the addressing capability of the processor.

19.       What is locality of reference?

          The effectiveness of the cache mechanism is based on a property of computer program called locality of reference.

          Many instructions in localized area of the program are executed repeatedly during some period, and the remainder of the program is accessed relatively infrequency.

20.       Define Set associative cache.

          In a set associative cache, a block can go in any one of a set of places in a cache. A set is a group of block in a cache.

21.       What is meant by block replacement?

          When a cache miss occurs, the controller must select a block to be replaced with the desired data. Only one block frame is checked for a bit and only that block can be replaced. This is called block replacement.

22.       List out advantages of write back cache.

          Write occur at the speed of clock

          Main memory bandwidth will be smaller when multiple writes occur to the same block.

23.       Give some methods to reduce cache miss penalty.

          Giving priority to read miss

          Using sub blocks to reduce fetch time

          Easily restart and critical word first

          Having second level caches

24.       Define memory refreshing.

          It is defined as the process of regarding the lost charge.

25.       What is spatial locality?

          There is a tendency for a process to make reference to a portion of the virtual address space in the neighborhood of the last reference.

26.       Define miss penalty.                                                              [AU-MAY 2012]

          The time to determine hit/miss, update cache (transfer new block of instructions or data) and access time.

27.       Differentiate write-through and write-back update methods in cache   memory.                                                                        [MAY/JUNE 2010]

                      Write back-update the cache memory along with main memory.

Write through-writing in cache only, equivalent copy is produce in main memory, when word is not updated from a long time.

28.       Write the functions of translation lookaside buffer. [MAY/JUNE 2010]

·         If we were to just cache the entries, it would still take us several

     accesses to perform a virtual memory translation.

·         They'd be cache accesses instead of main memory accesses, which

     would help a lot, but we can do better than that.

·         So, instead of just caching the entries themselves, we'll cache the

     whole virtual memory translation. Rather than using the existing  

     cache, we'll add a new, specialized cache whose only purpose is to

     cache the translations.

·         This specialized cache is called a translation lookaside buffer or TLB

29.       How to handle the miss penalty in memory subsystem.

       [MAY/JUNE 2010]

                  A Write Buffer is needed between the Cache and Memory

–         Processor: writes data into the cache and the write buffer

–         Memory controller: write contents of the buffer to memory.

30.       Define virtual memory.

Virtual Memory: Data may be stored in physical memory locations that have addresses different from those specified by the program.

31.       What is meant by interleaved memory organization?

Consecutive words are placed in the consecutive modules. To access these words, access is made to several modules at the same time. This leads to faster access. This technique is called Memory Interleaving. Here the higher order bits refer to the word address in the module and the lower order bits refer to module number.

32.       What is an associative memory?

·            Accessed by the content of the data rather than by an address

·            Also called Content Addressable Memory (CAM)

33.       Discuss about the different types of ROMs.

1. PROM - Programmable ROM

2. EPROM - Erasable PROM

3. EEPROM - Electrically Erasable PROM

4. Flash Memory

34.       What is a write buffer? How is it useful?

When a write through protocol is used, each operation results in writing a new value into the main memory. If the processor must wait for the memory function to be completed, the processor is slowed down. To improve performance, a write buffer can be included for temporary storage of write requests.

35.       What is a TLB? What is its significance?

A small cache, called TLB is corporate into MMU for this purpose. The operation of TLB is same as the operation of cache. The contents of the TLB should be coherent with the contents of the page tables in the memory.

36.       Why does DMA have priority over the CPU when both request a memory

       transfer?

To transfer large blocks of data at high speed, Direct Memory Access is used. A special control unit may be provided to allow transfer of a block of data directly between an external device and the main memory.

37.          Draw the memory hierarchy diagram and mention about the size, cost and speed of operation of each block.

38.       Distinguish between the write – through and write – back policies

        pointing out their relative merits and demerits.

Write Through Protocol:

Cache location and main memory location are updated simultaneously.

Write Back Protocol:

Update only the cache location and mark it updated with an associated flag bit called ‘dirty bit or modified bit ‘.

The main memory location of the word is updated later, when the block containing this marked word is to be removed from the cache during a replacement.

                                               

WRITE THROUGH PROTOCOL (DEMERITS)	WRITE BACK PROTOCOL (DEMERITS)
Results is unnecessary write operations in the main memory when the word in cache is updated several times	Results in unnecessary write operations because when a cache block is written back to the memory, all words of the block are written back even if only a single word has been changed while the block was in cache.

39.       Distinguish between memory mapped I/O and programmed I/O.

MEMORY MAPPED I/O:

·            I/O devices and memory share the same address space (i.e.) instructions like ‘MOVE’ treat I/O buffers (DATAIN & DATAOUT) as memory locations

·            Here to transfer data from DATAIN to Register R0, the following instruction can be used

Move DATAIN,R0

PROGRAMMED I/O:

·         I/O devices and memory have different address spaces.

·         Hence to transfer from DATAIN or to DATAOUT, special instructions such as ‘In’ and ‘Out’ are used.

·         Here the processor repeatedly checks a status flag to achieve synchronization between the processor and an I/O device. This process of checking is called “Polling”.

40.          Define the term locality of reference.

             Locality of Reference

·            The references to memory at any given time interval tend to be

confined within a localized areas. This area contains a set of information and the membership changes gradually as time goes by.

·            The effective of the cache memory is based on locality of reference

(i)       Temporal

(ii)     Spatial

TEMPORAL LOCALITY:

Whereas an instruction / data is first needed, this item should be brought into the cache where it will hopefully remain until it is needed again.

SPATIAL LOCALITY:

Instead of fetching just one item from the main memory to cache, it is useful to fetch several items that reside at adjacent addresses.

16 marks

1.      Explain the various mapping functions used for mapping main memory blocks into cache memory

2.      Explain the virtual memory address translation and TLB with necessary diagrams.

3.      Explain the organization of magnetic disk in detail.

4.      Discuss the memory interleaving and give its advantages

5.      Give the basic cell of an associative memory and explain its operations. Show how associative memories can be constructed using basic cell.

6.      Explain the concept of memory hierarchy.

7.      Describe the working principle of RAM, ROM and cache memories. Compare them based on their speed, cost and size.

8.      Give the structure of semiconductor RAM memories. Explain the Read and Write operation in detail.

9.      Write a short note on secondary storage devices in computer system.

10.  Describe Memory Interleaving and the addressing of multiple modules Memory system.

UNIT-V

1.              State advantages of a bus.

Versatility:

Ø          New devices can be added easily

Ø          Peripherals can be moved between computer systems that use

      the same bus standard

Low Cost:

Ø          A single set of wires is shared in multiple ways

              Manage complexity by partitioning the design

2.              State disadvantages of a bus.

It creates a communication bottleneck

Ø          The bandwidth of that bus can limit the maximum I/O

      throughput

The maximum bus speed is largely limited by:

Ø          The length of the bus

Ø          The number of devices on the bus

The need to support a range of devices with:

Ø             Widely varying latencies

Ø             Widely varying data transfer rates

3.              What is the General Organization of a bus?

          Control lines:

Signal requests and acknowledgments

Indicate what type of information is on the data lines

Data lines carry information between the source and the  

destination:

Ø       Data and Addresses

Ø       Complex commands

4.              How can you classify buses?

          Major criteria are:

                   Purpose (Processor-Memory Bus, I/O Bus, Backplane Bus)

                   Clocking (Synchronous, Asynchronous)

                   Data Transfer Mode (Parallel, Serial)

5.              Explain where synchronous buses can be used.

          Advantage: involves very little logic and can run very fast

          Disadvantages:

Ø       Every device on the bus must run at the same clock rate

Ø       To avoid clock skew, they cannot be long if they are fast

          Hence can be used in

Ø       processor-memory buses

Ø       Backplane buses when the bus length is short and there are few but high-speed I/O devices.

6.              Explain where asynchronous bus can be used.

          It can accommodate a wide range of devices

          It can be lengthened without worrying about clock skew

          It requires a handshaking protocol

          Hence can be used in I/O buses.

7.           What is meant by Vectored Interrupts?

Ø       A device requesting and interrupt may identify itself directly to the processor

Ø       It supplies a code to the processor that may represent the starting address of the interrupt service routine for the device

Ø       In some cases only few bits are supplied and the remaining bits are fixed

Ø       To accommodate a larger number of devices, each code can be assigned to a group of devices

Ø       The interrupt service routine can identify the device by ling the devices in the group

Ø       This arrangement implies that the service routine must always start at the same location

8.           Explain the following parameters

1. Propagation Delay: The time taken for the signal to travel from one point to another point on the bus.

2. Bus Skew: Skew occurs when two signals simultaneously transmitted from one source arrive at the destination at different times. This is because different lines of the bus may have different propagation delays.

3. Maximum propagation delay: In case of synchronous circuits bus skew is accounted as part of the maximum propagation delay.

4. Address Decode Time: Time taken to decode address and generate a device-selected signal if selected.

5. Setup Time and Hold Time: There is a critical period around the transition of the clock state where input data should be stable.  The period before the transition is called setup time. In case of a negative edge-triggered flip-flop, this the period before the clock goes to ‘0’ state. The period after the transition is called the hold time. The setup time is also the time that data should be present at the input of a circuit to be recognized.

6. Access Time: Time taken for the target to fetch requested data from DATAIN register and place it on the bus, from the time the gating signal (Clock or Master Ready) is received by the target.

9.           What is meant by Interrupt nesting?                    [NOV/DEC 2011]

Ø          I/O devices should be organized in a priority structure

Ø          An interrupt request from a high priority device should be accepted  

      while the processor is servicing another request from a low priority

      device

Ø          The priority level of the processor is the priority level of the program

      it is executing

Ø          The processor accepts interrupts only from devices that have higher  

      priority than its own

Ø          The processor’s priority is usually encoded in a few bits of the

      processor status word

Ø          It can be changed by a program instruction that writes into the PS

10.       What is meant by debugging?

Ø          The debugger uses exceptions to provide trace mode and 

      breakpoints

Ø          When a processor is operating in the trace mode, an exception  

      occurs after every instruction

Ø          Breakpoints: the program is interrupted at specific points selected by

      the user

Ø         An instruction called trap or software interrupt is used to specify breakpoints

11.          What are the uses of interrupt in OS?    [AU-Nov 2008]

Ø          Application programs request services from the OS using traps (also

      called software interrupts)

Ø          Most processors have several different software interrupts

Ø          Each software interrupts has its own vector code

Ø          These instructions can be used to call different parts of the OS

12.          Define Multitasking.                                               [AU-MAY 2012]

Ø          The processor executes several user program at the same time

Ø          Each program runs for a short period of time called slice

Ø          Time slicing is one implementation of multitasking

13.          Name the three states in a process.

Ø          Running

Ø          Runnable: program is ready for execution but is waiting to be

      selected by the scheduler

Ø          Blocked: the program is not ready to resume execution

14.          Name the sources for exceptions.

          There are five sources for exceptions

Two are external request lines: IRQ and FIQ (Fast Interrupt Request)

One software interrupt (SWI)

Two exceptions that may be caused by abnormal conditions during program execution

                   Exceptions are handled according to the following priority

·         Reset( highest priority)

·         Data abort

·         FIQ

·         IRQ

·         Prefetch abort

·         Undefined instruction (lowest priority)

    Reset overrides all other conditions to bring the processor to a known       starting condition

15.          Define Bus protocol.                                                          [Nov/Dec 2011]

          A bus protocol: set of rules that govern the behavior of the devices connected to the bus and when to place information on the bus, assert control signals, ect …

16.          Define Elapsed time and Processor time

          "Elapsed Time" - Total time required to execute the program

          "Processor Time" - Sum of the periods during which the processor is active.

17.          What is DMA?

·               DMA is direct memory access

·               Special request lines like Dreq, Ireq eliminate the need of CPU to

       check the status of IO devices.

·               No need of execution of instructions by the CPU.

18.          Mention the advantages and disadvantage of Programmed I/O

Advantage:

          Simple: the processor is totally in control and does all the work

Disadvantage:

          Polling overhead can consume a lot of CPU time

19.          Define DMA Controller.

          DMA controller is usually located on the motherboard. It can access the system bus independent of CPU. It contains several registers that can be read and written by the CPU

·      Memory address register

·      Byte count register

·      I/O port to use

·      Direction of Transfer

·      Transfer Unit (byte or word)

·      Burst size (Number of bytes to transfer in one burst)

20.          Differentiate Synchronous and Asynchronous bus.

           Synchronous Bus:

·      Includes a  clock in the control lines

·      A fixed protocol for communication that is relative to the clock

 Advantage: involves very little logic and can run very fast

 Disadvantages:

·      Every device on the bus must run at the same clock rate

·      To avoid clock skew, they cannot be long if they are fast

            Asynchronous Bus:

·      It is not clocked

·      It can accommodate a wide range of devices

·      It can be lengthened without worrying about clock skew

·      It requires a handshaking protocol

21.          Why interrupt masks provided in a processor?           [AU -May, 2006]

          Maskable interrupts are enabled and disenabled under the program  control. By setting the flip-flops in a processor, interrupts can be masked or unmasked. When masked, processor does not response to the interrupt.

22.          Mention the advantages of USB bus. [AU - May 2009]

        [MAY/JUNE 2013]

·         Simple connectivity and cables

·         One interface for many devices

·         Automatic configuration and No user setting

·         Frees hardware resources for other devices

·         Install or remove a peripheral regardless of the power state

·         Reliability and low cost and power consumption

23.          Compare memory mapped and I/O mapped I/O. [MAY / JUNE 2013]

          Memory mapped I/O:

·         Memory and I/O share the entire address range of processor

·         Processor provides ore address line for accessing memory. Therefore more decoding is required control signals

·         Memory controls signals are used to control read and write I/O   

     operations.

24.          What is priority interrupt?                                    [AU may 2008]

          When interrupt requests arrive from two more devices simulates the processor has to decide which request should be serviced first and which one delayed. The processor takes the decision with the help of interrupt priorities.

25.          Differentiate serial and parallel port.     [AU Nov 2008]

          Serial port:

1. Used to connect the processor to I/O devices that requires transmission of data one bit at a time.

2. Serial interface is universal asynchronous receiver transmitter.

Parallel port:

1. Used to connect the parallel to I/O devices that require transmission of data simultaneously.

2. The interface circuit is connected to an asynchronous bus on which transfer controlled using hand shake controls.

26.          What is cycle stealing?                             [AU – May 2012]

          Cycle stealing is used to describe the "stealing" of a single CPU cycle to allow a DMA engine to perform a DMA operation. This is opposed to block operation where a DMA engine would request a bus, hold it for a complete transaction (typically 16-32 bytes but could last much longer) before releasing to a CPU.Cycle stealing generally occurs when the entire DMA transfer of data is finished, the DMA controller interrupts the CPU.

27.          What is the difference between a subroutine and an interrupt service

         routine?                                                                     [MAY/JUNE 2010]

Subroutine is a portion of code within a larger program, which performs            

           a specific task and is relatively independent of the remaining code.

Interrupt Service Routines (ISRs) are to handle hardware interrupts.

           These routines are not independent threads, but more like signals. ISR is  

           called if any thread is suspended by an interrupt.

28.          State the importance of DMA.                                         [MAY/JUNE 2010]

NETDMA provides services for offloading the memory copy operation performed by the networking subsystem, when receiving network packets, to a dedicated DMA engine.

           

29.          Write the function of bus arbiter in DMA interface.     [MAY/JUNE 2010]

A bus arbitration interface comprises first and second serial/parallel converting units connecting a DMA device to an LSI with a DMA controller built therein for exchanging a request signal sent from the DMA device to the DMA controller and an acknowledge signal sent from the DMA controller to the DMA device as serial signals, a DMA arbitration bus interface, that is an outside interface of the LSI, provided with signal I/O pins and a DMA device arbitration interface that is an outside interface of the DMA device.

30.             What are the advantages of using USB based devices.        [MAY/JUNE 2010]

·         A USB flash drive is a NAND type flash memory.

·         The USB drive is made up of secure case small circuit board and is

     integrated with a universal serial bus connector

·         The USB drive can be easily inserted into the USB port of the

     computer.

·         The USB drives are more reliable when huge amounts of data has to

  be moved.

31.          List the function of I/O interface.                                   [MAY/JUNE 2010]

Low-level The low-level interface provides basic open and close functions for       files and devices.

Stream The stream interface provides read and write I/O for pipes and FIFOs.

Terminal The terminal interface provides formatted output and buffering.

Asynchronous The asynchronous interface provides concurrent I/O and processing.

Input Language The input language interface uses the lex and yacc commands to generate a lexical analyzer and a parser program for interpreting I/O.

32.          What is meant by SCSI bus? How the controller of SCSI bus is

         classified?                                                                 [NOV/DEC 2011]

SCSI is an acronym for Small Computer Systems Interface. It is an ANSI standard that has become one of the leading I/O buses in the computer industry.

Classification:

1.      FWD: Fast Wide Differential

2.      FND: Fast Narrow Differential

3.      SE: Single Ended

4.      FN: Fast Narrow

33.          What is an interrupt?                                         [NOV/DEC 2011]

Interrupt is generally said to be an signal passed by an i/o devices for data transfer purpose. The microprocessor accepts the interrupt signal does the job.
Eg: Consider a c d device sends an interrupt signal to microprocessor to transfer the data to hard disk.

43.          List out the types of interrupt.

·         Hardware Interrupts

·         Software Interrupts

44.          What is DMA?

To transfer large blocks of data at high speed, Direct Memory Access is used. A special control unit may be provided to allow transfer of a block of data directly between an external device and the main memory.

45.          What are the different modes of I/O transfer available?

There are 2 types of ports

·         Serial Port

·         Parallel port

Serial port: Transmits data one bit at a time.

Parallel port: Transfers data in the form of number of bits (for 16) simultaneously to or from the device.

46.          Distinguish between horizontal and vertical microprogramming  organizations.

HORIZONTAL ORGANIZATION	VERTICAL ORGANIZATION
1. Minimally Encoded scheme in which many resources can be controlled with a single micro instruction.	1. Highly encoded scheme that use compact codes to specify only a small number of control functions in each microinstruction.
2. Used when a higher operating speed is desired.	2. Slower operating speed, because more microinstructions are needed to perform the described control functions.
3. Used when the machine allows parallel use of resources.	3. Does not imply that the total number of bits in the control store is smaller. Means that less hardware is needed to handle the execution of microinstructions.

47.             Write about memory mapped I/O and programmed I/O.

MEMORY MAPPED I/O:

·         I/O devices and memory share the same address space (i.e.)  

                  instructions like ‘MOVE’ treat I/O buffers (DATAIN & DATAOUT) as  

                  memory locations

·         Here to transfer data from DATAIN to Register R0, the following

     instruction can be used

Move DATAIN,R0

PROGRAMMED I/O:

·            I/O devices and memory have different address spaces. Hence to

      transfer from DATAIN or to DATAOUT, special instructions such as    

     ‘In’ and ‘Out’ are used.

·            Here the processor repeatedly checks a status flag to achieve

      Synchronization between the processor and an I/O device. This        

      process of checking is called “Polling”.

48.             Differentiate Isolated I/O from Memory mapped I/O.

Isolated I/O

·            Separate I/O read/write control lines in addition to memory   

      read/write control lines

·            Separate (isolated) memory and I/O address spaces

·            Distinct input and output instructions

                   Memory mapped I/O

·            A single set of read/write control lines (no distinction between

      memory and I/O transfer)

·            Memory and I/O addresses share the common address space 

      reduces memory address range available

·            No specific input or output instruction

·            The same memory reference instructions can be used for I/O   

      transfers

·            Considerable flexibility in handling I/O operations

49.             Distinguish between a synchronous bus and an asynchronous bus.

Synchronous bus:

·            In synchronous bus, all devices derive timing information from a

      common clock line.

·            Equally spaced pulses on this line define equal time intervals.

·            Each of these intervals constitutes a bus cycle, during which one

      data transfer can take place.

Asynchronous Bus:

·            Under this scheme, handshaking is used. 

·            The common clock is replaced by two timing control lines, Master-

      ready and Slave-ready.

50.             How does a processor handle an interrupt?

·            An I/O device can communicate with a processor by raising

      interrupts. These Interrupts alert the processor that the I/O device  

      is ready.

·            The I/O device can interrupt by sending a hardware signal called

      ‘Interrupt’. At least one of the bus control lines called ‘Interrupt-

       Request’ line is dedicated for this purpose.

·            Processor executes a routine (function) in response to an

      interrupt. This routine is called Interrupt Service Routine (ISR).

·            As a part of handling interrupts, the processor must inform the  

device that its request has been recognized so that it may remove  its interrupt-request signal. This is done by a special signal called interrupt – acknowledge signal.

51.             What are the functions of a typical I/O interface?

An I/O interface consists of the circuitry required to connect an I/O device to a computer bus.  On one side of the interface, we have the bus signals for address, data and control. The other side is called port, which has a data path with its associated controls to transfer data between the interface and the I/O device.  There are 2 types of ports

·         Serial Port

·         Parallel port

52.             How does the processor handle an interrupt request?

As a part of handling interrupts, the processor must inform the device   

  that its request has been recognized so that it may remove its interrupt-

   request signal. This is done by a special signal called interrupt – acknowledge

   signal.

53.             When DMA and interrupt are processed by CPU?

To initiate the transfer of a block of words, the processor sends the  

starting address, the number of words in the block and direction of the transfer. On receiving this information, the DMA controller proceeds to perform the requested operation. When the entire block has been transferred, the controller informs the processor by raising an interrupt signal.

54.             How does bus arbitration typically work?

A conflict may arise if both the processor and a DMA controller or 2 DMA

controller try to use the bus at the same time to access main memory. To resolve these conflicts, an arbitration procedure is implemented on the bus to coordinate the activities of all devices requesting memory transfers.

55.             What are the two major advantages and disadvantages of the bus?

·         The processor, main memory and I/O devices are interconnected by means of a bus whose primary function is to provide a communication path for the transfer of data.

·         The bus includes the lines needed to support interrupts and arbitration.

·         A bus protocol is a set of rules that govern the behavior of various devices connected to the bus.

The bus lines are of three types

·      Data

·      Address

·      Control

The bus control signals also carry timing information. A variety of schemes have been devised   for the timing of the data transfers over a bus.

These are classified as

·Synchronous.

·Asynchronous.

16 marks

1. Explain the use of vectored interrupts in processors. Why is priority handling desired in interrupt controllers? How do the different priority schemes work?
2. Explain how DMA transfer is accomplished with neat diagram.
3. Describe the functions of SCSI with a neat diagram.
4. Explain the functions to be performed by a typical I/O interface with a typical input or output interface
5. Discuss the operation of any two input devices
6. Explain how I/O devices can be interfaced with a block diagram.
7. Explain in detail about interrupt handling
8. Explain in details about standard I/O interfaces.
9. Describe the working principles of USB.
10. Compare the characteristics of SCSI and PCI.

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2010

Fourth Semester

Computer Science and Engineering

CS2253 — COMPUTER ORGANIZATION AND ARCHITECTURE

(Common to Information Technology)

(Regulation 2008)

Time: Three hours Maximum: 100 Marks

Answer ALL Questions

PART A — (10 × 2 = 20 Marks)

1. Distinguish between autoincrement and autodecrement addressing mode.

2. Compare RISC with CISC architecture.

3. Under what situations the micro program counter is not incremented after a new instruction is fetched from micro program memory?

4. What are the relative merits of horizontal and vertical microinstruction format?

5. What is pipelining and what are the advantages of pipelining?

6. List the key aspects in gaining the performance in pipelined systems.

7. How many memory chips are needed to construct 2 M × 16 memory system using 512 K × 8 static memory chips?

8. What is virtual memory and what are the benefits of virtual memory?

9. What is meant by bus arbitration?

10. Name and give the purpose of widely used bus standard.

PART B — (5 × 16 = 80 Marks)

11. (a) (i) Describe the role of system software to improve the performance of a computer. (Marks 8)

(ii) Design a 4-bit adder/subtracter circuit using full adders and explain its function. (Marks 8)

Or

(b) (i) What are the special registers in a typical computer? Explain their purposes in detail. (Marks 8)

(ii) Design a 4-bit fast adder and explain its function in detail. (Marks 8)

12. (a) (i) Draw and explain the block diagram of a complete processor. (Marks 6)

(ii) Briefly describe the design of a hardwired control unit. (Marks 10)

Or

(b) (i) Explain the basic organization of a microprogrammed control unit and the generation of control signals using microprogram. (Marks 12)

(ii) What are the advantages and disadvantages of hardwired and microprogrammed control? (Marks 4)

13. (a) (i) Describe the role of cache memory in pipelined system. (Marks 8)

(ii) Discuss the influence of pipelining on instruction set design. (Marks 8)

Or

(b) What is instruction hazard? Explain the methods for dealing with the instruction hazards. (Marks 16)

14. (a) (i) What are the different secondary storage devices? Elaborate on any one of the devices. (Marks 8)

(ii) Explain how the virtual address is converted into real address in a paged virtual memory system. (Marks 8)

Or

(b) (i) Explain approaches for addressing multiple-module memory systems with suitable diagrams. (Marks 6)

(ii) Briefly describe magnetic disk principles and also the organization and accessing of data on a disk. (Marks 10)

15. (a) (i) Describe the hardware mechanism for handling multiple interrupt requests. (Marks 8)

(ii) What are handshaking signals? Explain the handshake control of data transfer during input and output operation. (Marks 8)

Or

(b) (i) What are the needs for input-output interface? Explain the functions of a typical 8-bit parallel interface in detail. (Marks 10)

(ii) Describe the USB architecture with the help of a neat diagram. (Marks 6)

Anna University
B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010

Fourth Semester

Computer Science and Engineering

CS 2253 — COMPUTER ORGANIZATION AND ARCHITECTURE

(Common to Information Technology)

(Regulation 2008)

Time : Three hours Maximum : 100 Marks

Answer ALL questions

PART A — (10 × 2 = 20 Marks)

1. What does the term hertz refer to?
2. How is the number 25 represented in BCD and ASCII code?
3. What is mono phase?
4. What are the two possible error conditions that may arise in a stack operation?
5. How can memory access be made faster in a pipelined operation? Which hazards can be reduced by faster memory access?
6. How do you calculate the execution time T of a program that has a dynamic instruction count N?
7. What is memory interleaving?
8. How is disk access time calculated?
9. What are Priority groups?
10. What are the operating system routines of a keyboard driver?

 PART B — (5 × 16 = 80 Marks)

11. (a) (i) Describe the connections between the processor and memory with a neat structure diagram. (Marks 8)
(ii) X=A X B + C X C (Marks 8)
Explain how the above expression will be executed in one address, two address and three address processors in an accumulator organization.
                                                Or
(b) Explain in detail how Instructions are encoded. (Marks 16)
12. (a) (i) Draw the diagram of the single Bus Organization of the data path inside a processor. (Marks 8)
(ii) Explain the above regarding execution. (Marks 8)
                                                Or
(b) (i) Explain the Organization of the control unit to allow conditional branching in the microprogram. (Marks 8)

(ii) How is a functional field micro instruction generated? Explain. (Marks 8)
13. (a) Explain how the instruction pipeline works. What are the various situations where an instruction pipeline can stall? What can be its resolution? (Marks 16)
                                                Or
(b) (i) Examine the relationships between pipeline execution and addressing modes. (Marks 8)
(ii) What do you mean by out of order execution? (Marks 8)
14. (a) Write a note on Asynchronous and Synchronous DRAMs. (Marks 16)
                                                Or
(b) (i) Analyze the memory hierarchy in terms of speed, size and Cost. (Marks 8)
(ii) Explain the Address Translation in Virtual Memory. (Marks 8)
15. (a) Explain the following:
          (i) Memory mapped I/O (Marks 4)
          (ii) I/O Registers (Marks 4)
          (iii) Hardware Interrupts (Marks 4)
          (iv) Vectored interrupt (Marks 4)
                                                Or
(b) Write a note on SCSI BUS. Explain with a neat diagram. (Marks 16)

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011

Fourth Semester

Computer Science and Engineering

CS 2253 - COMPUTER ORGANIZATION AND ARCHITECTURE

(Common to Information Technology)

(Regulation 2008)

Time: Three hours                                                              Maximum: 100 marks

Answer ALL questions

PART A - (10 x 2 = 20 marks)

1. What is an opcode? How many bits are needed to specify 32 distinct operations?

2. Write the logic equations of a binary half adder.

3. Write the difference between Horizontal and Vertical Microinstructions.

4. In what ways the width and height of the control memory can be reduced?

5. A = 5 A= 3+A, B= 4xA What hazard does the above two instructions create when executed concurrently?

6. What are the disadvantages of increasing the number of stages in pipelined processing?

7. What is the use of EEPROM?

8. State the hardware needed to implement the LRU in replacement algorithm.

9. What is distributed arbitration?

10. How interrupt requests from multiple devices can be handled?

PART B - (5 x 16 = 80 marks)

11. (a)With examples explain the Data transfer, Logic and Program Control Instructions? (16)

Or

(b) Explain the Working of a Carry-Look Ahead adder. (16)

12. (a) (i) Describe the control unit organization with a separate Encoder and Decoder functions in a hardwired control. (8)

(ii) Generate the logic circuit for the following functions and explain. (8)

Or

(b) Write a brief note on nano programming. (16)

13. (a) What are the hazards of conditional branches in pipelines? how it can be resolved? (16)

Or

(b)Explain the super scalar operations with a neat diagram. (16)

14. (a)What is a mapping function? What are the ways the cache can be mapped? (16)

Or

(b) Explain the organization and accessing of data on a Disk. (16)

15. (a) (i) How data transfers can be controlled using handshaking technique? (8)

           (ii) Explain the protocols of USB. (8)

Or

(b) How the parallel port output interface circuit works? (16)

B.E./B.Tech DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.

Fifth Semester

Electronics and Communication Engineering

EC 2303 — COMPUTER ARCHITECTURE AND ORGANIZATION

(Common to Sixth Semester Biomedical Engineering)

(Regulation 2008)

(Common to PTEC 2303 – Computer Architecture and Organization for B.E.

(Part-time) Electronics and Communication Engineering

Fourth Semester Regulation – 2009)

Time : Three hours Maximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

1. Define priority encoder.

2. What are the factors to be considered in selecting a number representation

to be used in a computer?

3. Write down the equation for carry generate and propagate.

4. Define coprocessor.

5. Compare the two methods to design the hardwired controller.

6. What is the use of micro assembler?

7. What is DRO and NDRO?

8. What is temporal locality?

9. What are the limitations of programmed IO?

10. Write down the CPU steps to determine the status of IO device.

PART B — (5 × 16 = 80 marks)

11. (a) (i) Draw the block diagram of a 4 bit register level magnitude comparator and explain. (8)

(ii) Briefly explain the organization of IAS computer with its instruction set. (8)

Or

(b) (i) How does one detect and correct errors during data transmission ? (8)

(ii) Describe in detail the different kinds of addressing mode with an example. (8)

12. (a) Explain 2’s complement multiplier with a neat block diagram. (16)

Or

(b) Explain floating point adder pipeline with neat block diagram. (16)

13. (a) (i) Write short notes on Nano programming. (8)

(ii) Describe the characteristics of supper scalar processing. (8)

Or

(b) Design a micro programmed control unit of non-pipelined general purpose computers (16)

14. (a) Describe in detail magnetic tape memories and disk memories. (16)

Or

(b) Describe cache memory in detail. (16)

15. (a) (i) What is DMA? Draw the block diagram and explain it in detail.(8)

(ii) Describe vectored interrupt scheme with a neat block diagram.(8)

Or

(b) (i) Define fault tolerance. How is it related to redundancy? Explain different approaches for designing fault tolerance systems. (8)

(ii) Explain different types of bus arbitration scheme. (8)